The present invention relates to signal generation, and, more particularly, to deriving one or more lower frequency signals from a higher frequency clock signal.
Conventional signal generators may use multiple oscillators to derive harmonic frequency signals from a clock signal. Unfortunately, this may result in a relatively large number of oscillators; therefore, in practice, only a subset of the harmonic frequencies is typically provided.
Other conventional signal generators may generate signals having frequencies that are not sub-harmonics of a clock signal through the use of alternate ratio counters. These signal generators may use the clock signal to drive two counters whose count differs by one. By alternately combining the outputs of these two counters in an appropriate pattern, a waveform may be generated having a desired average frequency and an edge jitter approximately equal to a cycle of the clock signal. Such signal generators, however, may be less desirable for use in generating a large number of different frequencies as a set of counter ratios and a pattern would typically have to be stored for each frequency to be generated.
Still other conventional signal generators may generate signals by adding a number to a running sum. The adder overflow is a pulse train at the desired frequency. These signal generators, however, typically use an adder with a large number of bits to operate at the generally high clock frequency rate. This may require high-speed logic to generate signals with fine edge jitter. The generated frequencies are the multiple of a binary divisor of the clock signal frequency. More complex logic may be used to allow additional frequencies to be generated beyond the binary divisors of the clock signal frequency. This complex logic, however, operates at the high clock signal frequency.